Technical Field
The disclosure in generally relates to a high-density memory device method for fabricating a memory device, and more particularly to a memory device with a three dimensional (3D) memory cells array and the method for fabricating the same.
Description of the Related Art
As the development of electrical technology, semiconductor memory devices have being broadly applied to various electronic products, such as MP3 players, digital cameras, notebooks, cell phones, etc. In order to accommodate the rising demand for reducing the size of the electronic products and improving the operation speed thereof, a 3D memory device having a higher density memory and excellent electrical characteristics, e.g. reliability in data storage and high operating speed, has been provided.
A typical 3D semiconductor memory device has a 3D memory cells array using surrounding gate transistor (SGT) configured in a multi-layer stack structure and a plurality of string select line (SSL) transistors connected in series with the 3D memory cells array. In order to reduce the size of the 3D semiconductor memory device to provide a higher density memory, it is necessary not only to reduce the size of the SGT but also to reduce the size of the SSL transistors. However, the SSL transistors conventionally implemented by field effect transistors (FET) having horizontally oriented gate which occupy large footprint and may limit the size reduction of the 3D semiconductor memory device.
Recently, bipolar junction transistors or diodes having smaller lateral footprint are applied to taking the place of the conventional horizontally oriented gate FET to serve as the SSL transistors of the 3D semiconductor memory device. However, it is hard to control the bipolar junction transistors or the diodes in a multi-bit operation due to the fact that the characteristic electrical current-voltage (I/V) curve is exponential.
Therefore, there is a need of providing an improved 3D semiconductor memory device and method for fabricating the same to obviate the drawbacks encountered from the prior art.